A Power Efficient Fully Adiabatic Logic Circuit Design Approach: Application to Inverter and 8421 to Excess-3 Code Converter

Abstract Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype a power-efficient standard or fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design compared with traditional complementary metal oxide semiconductor (CMOS) as well two popular fully adiabatic logic families: dynamic CMOS (ADCL) and phase clocked static (2PASCL). investigation was conducted at frequencies ranging from 100 900 MHz. circuit employs 0.3 μ m technology, channel length width set 0.75 m, respectively. savings 500 MHz when logic, ADCL, 2PASCL are 54.54%, 28.57%, 16.67%,